TTTC: DRVW 2011 Call for Participation

CALL FOR PARTICIPATION

Scope -- Venue -- Workshop Registration -- Advance Program -- More Information -- Committees

Scope

As silicon based CMOS technologies are fast approaching their ultimate limits, reliability is threatened by issues such as process, voltage and temperature variability, accelerated aging and wearout, radiation induced soft-errors and cross talk. In particular, variability of process, voltage and temperature represent a significant threat not only for parametric yield but also for reliability, since they induce timing faults that are extremely difficult to detect during manufacturing testing. It results on increasing ratio of circuits passing fabrication test that are susceptible to manifest failures in the field.

These problems are creating barriers to further technology scaling and are forcing the introduction of new process, design and test solutions aimed at maintaining acceptable levels of reliability. As elimination of these issues is becoming increasingly difficult, various design techniques are emerging to circumvent them. These techniques may incur area, power, yield or performance penalties. Thus, to enable their adoption by the industry there is need for novel solutions to minimize penalties and provide automation tools.

The goal of this workshop is to create an informal forum to discuss those design, EDA and test innovations enabling chips to maintain acceptable reliability levels at reasonable cost.

The Venue

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Laguna Cliffs Marriott Resort California
Perched atop the cliffs of Dana Point, along the beautiful Southern California coast, the Laguna Cliffs Marriott Resort & Spa, provides an oceanside escape like no other.

Workshop Registration

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VTS Registration You may register for DRVW 2011 through the VTS 2011 online registration website.

Hotel reservation You may make hotel reservations through the VTS 2011 online hotel reservation website.

Advance Program

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Wednesday -- Thursday

May 4, 2011 (Wednesday)

4:00 PM - 6:30 PM	OPENING SESSIONS
4:00 - 4:15	Opening Remarks Michael Nicolaidis, General Co-Chair Yervant Zorian, General Co-Chair Virendra Singh, Program Co-Chair
4:15 - 5:00	Keynote 1 Speaker: Melvin Breuer (Univ. of Southern California) Topic: The Three R's: Reliability, Redundancy, and Reconfigurability
5:00 - 5:30	Invited Talk 1 Speaker: Tim Cheng (Univ. Of California, Santa Barbara) Topic: DfX in the Late-Silicon Era
5:30 - 6:00	BREAK
6:00 - 6:30	Invited Talk 2 Speaker: Abhijit Chattrejee (Georgia Tech) Topic: Variability and Mixed Signal Design

7:00 PM SOCIAL EVENT

May 5, 2011 (Thursday)

8:00 AM - 9:30 AM	Keynote Sessions
8:00 - 8:30	Keynote 2 Masahiro Fujita (Tokyo University) Topic: Patchable Hardware Design
8:45 - 9:30	Keynote 3 Diana Marculescu (Carnegie Mellon University) Topic: Symbolic Reliability Modeling, Analysis, and Optimization

9:30 AM - 10:30 AM	SESSION 1
1.1	Criticality of Configuration Bits in SRAM-based FPGAs: Predictive Analysis and Experimental Results Lorena Anghel, Jean-Baptiste Ferron, and Regis Leveugle (TIMA, France)
1.2	Variability-aware Task mapping strategies for Many-cores processor chips Fabien Chaix, Gilles Bizot, Michael Nicolaidis, and Nacer-Eddine Zergainoh (TIMA, France)

10:30 - 11:00 AM BREAK

11:00 AM - 12:00 PM	SESSION 2: Invited Talks
2.1	Speaker: Kanak Agrawal (IBM) Topic: Addressing Process Variability Challenges through better Coupling between Design and Technology
2.2	Speaker: Adit Singh (Auburn University) Topic: Detecting Reliability Defects within Random Parameter Variation

12:00 - 1:45 PM LUNCH

1:45 PM - 2:45 PM	SESSION 3: Invited Talks
3.1	Speaker: Cecilia Metra (Univ. Of Bologna) Topic: Processor Parameter & Clock Variation: How We Can Deal with Them in High Performance Microprocessors
3.2	Speaker: Speaker: Abhilash Goyal Topic: Self-Calibrating Architectures for Low-Cost and High-Yield Systems

2:45 PM - 4:15 PM	Panel: Variability and Reliability: Will they Get Better or Worse in Future CMOS Technologies? Moderator: Subhasis Mitra (Stanford University)
	Participants: Peter Koeppen, TI Puneet Gupta, UCLA TBD TBD TBD

4:15 PM WRAP-UP

More Information

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General Information

Michael Nicolaidis
TIMA Laboratory
Tel: +33476575060
Email: michael.nicolaidis@imag.fr

Yervant Zorian,
Synopsys
Tel: +1 (650) 584-7120
Email: zorian@synopsys.com

Program Information

Dimitris Gizopoulos
U. Piraeus
Tel: +30 210 414 2372
Email: dgizop@unipi.gr

Virendra Singh
IISc, Bangalore
Tel: +91-80-2293-3421
Email: viren@serc.iisc.ernet.in

Committees

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General Chairs
Michael Nicolaidis, TIMA
Yervant Zorian, Virage Logic

Vice General Chair
Adit Singh, Auburn U.
Rajesh Galivanche, Intel

Program Chair
Dimitris Gizopoulos, U. Piraeus
Virendra Singh, Indian Inst. of Science

Vice Program Chair
Sreejit Chakravarty, LSI

Finance Chair
Nacer-Edine Zergainoh, TIMA

Publicity Chair
Yiogos Makris, Yale U.

Panels Chair
Subhasish Mitra, Stanford U.

Publications Chair
Mihalis Psarakis, U. Piraeus

For more information, visit us on the web at: DRVW 2011

The 3rd IEEE Design for Reliability and Variability Workshop (DRVW 2011) is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC).